Gauging whether an electronic circuit may operate at the specified speed needs the ability to determine or calculate, during the design stage of the electronic design, the delays of the electronic circuit at various steps. The calculated delays may then be incorporated in various stages (e.g., logic synthesis, placement, routing, post-route optimizations, etc.) of the electronic design process to ensure that the electronic design may perform as designed at the specified speed. Although timing analyses may be performed with a rigorous circuit simulation, timing analyses such as static timing analysis (STA) are a method of computing the expected timing of an electronic circuit with fast and reasonably accurate results without requiring a simulation of the electronic circuit in its entirety in order to avoid the expensive cost in runtime. Timing analyses utilize timing models that provide, for example, timing information (e.g., timing attributes, timing constraints, etc.) and/or other description (e.g., cell description, bus description, environment description, etc.) for electronic design components.
For an electronic design component (e.g., a wide complex cell, a multi-bit cell, etc.) that includes multiple inputs, the number of timing models for each input of the electronic design component may be large. This large number of timing models may then be incorporated into the timing library and used in the timing analyses for the electronic design including the electronic design component. Nonetheless, such timing analyses may require significant runtime because delay calculations may need to perform a simulation for each timing model.
Therefore, there exists a need for a method, system, and computer program product for enhancing timing analyses with reduced timing libraries for electronic designs.